It is a goal of electronic designers to design circuits that utilize a low supply voltage and consume low power. This is the case for Analog to Digital Converters or ADC, and in particular, for sample and hold circuits used in analog to digital conversion which typically require very high sampling frequency to achieve good performance and accuracy. A high sampling frequency requirement typically results in high power consumption.
FIG. 1 is a prior art Analog to Digital Converter (ADC) 100 and a representative timing diagram 102. ADC 100 includes a traditional sample and hold circuit or SnH circuit 104. A pulse modulator 106 converts amplitude information of an input analog signal into time information by duty cycle modulation. The timing diagram 102 shows a pulse-modulated signal 108 which is generated by the pulse modulator 106, and received by the SnH circuit 104. The SnH circuit 104 samples the output of the pulse modulator 106 at discrete intervals of time (where the interval may be represented by FS) using an equidistant sampling clock. The output of the SnH circuit 104 is represented as sampled modulated signal 110. Pulses generated by the equidistant sampling clock are represented by signal 112.
Equidistant sampling can result in a duty cycle modulated square wave 110 with synchronous leading and trailing edges, similar to the modulated signal 108. The difference between the edge positions of the modulated signal 108 and the sampled signal 110 is an introduced quantization noise as represented by signal 114.
Various known techniques may reduce the quantization noise depicted in signal 114. Such techniques include applying higher clock frequencies that use a polyphase sampler and polyphase filters instead of the SnH 110 circuit. However, these techniques are usually complex, and inefficient in reducing the high sampling clock required for sampling the analog signal. Therefore, such known techniques still may require a high supply voltage, and consume relatively more power.